Phase-locked loop slip detector

A lock-slip detect circuit for a phase-locked loop (PLL), comprising:

• a low pass filter (LPF) having an LPF input and an LPF output, the LPF input configured to receive a first signal comprises pulses having pulse widths indicative of a phase difference between clock signals;
• a flip-flop having a clock input and a flip-flop output, the clock input coupled to the LPF output;
• and
• a lock-slip control circuit coupled to the flip-flop output, the lock-slip control circuit configured to determine phase-lock and phase-slip based at least in part on a signal on the flip-flop output.

A phase-locked loop (PLL), comprising:

• a voltage-controlled oscillator (VCO) having a VCO output configured to generate an output clock;
• a phase-frequency detector (PFD) having a first PFD input, a second PFD input, and a PFD output, the first PFD input configured to receive a reference clock, the second PFD input coupled to the VCO output, the PFD configured to generate a first signal on the PFD output, the first signal comprising pulses having pulse widths indicative of a phase difference between the reference clock and the output clock;
• and
• a lock-slip detect circuit coupled to the PFD, the lock-slip detect circuit configured to determine phase-slip based at least in part on the first signal, wherein the lock-slip detect circuit includes:
• a low pass filter (LPF) having an LPF output;
• a flip-flop having a clock input, a flip-flop input, and a flip-flop output, the clock input coupled to the LPF output;
• and
• a lock-slip control circuit coupled to the flip-flop output, the lock-slip control circuit configured to:
• assert a lock signal indicating phase-lock between the output clock and the reference clock responsive to no edges being detected on the flip-flop output for a predetermined number of cycles of the reference clock;
• and
• assert a quasi slip signal responsive to at least one edge being detected on the flip-flop output while the lock signal is asserted.