Mixed signal computer
AssigneeOctavo Systems LLC
InventorsLaurence Ray SIMAR, Jr., Erik James WELSH, Peter LINDER, Gene Alan FRANTZ
Life of this patent
Estimating the term…
Abstract
The present disclosure describes a mixed signal computer unit using a combination of analog and digital components/elements in a cohesive manner. Depending on the signals and data that need to be processed, the analog processing elements and digital processing elements may be used separately, independently or in combination to optimize the computational results and the performance of the computation. Operations may be controlled by one or more digital cores.
Claims23
A mixed signal computer, comprising:
- at least one re-configurable analog processing array (RAPA);
- at least one programmable digital core array (PDCA);
- and
- one or more communication paths between said at least one RAPA and at least one PDCA.
(canceled)
A mixed signal computer, comprising:
- a re-configurable analog array comprising a plurality of analog components and a first plurality of digital components, wherein at least a portion of i) said plurality of analog components and ii) said first plurality of digital components is configurable to form a connected network arranged to perform at least one selected analog processing function on an analog signal supplied to said re-configurable analog array;
- and
- a re-configurable digital array comprising a second plurality of digital processing units, wherein
- the re-configurable digital array comprises a first portion and a second portion,
- the first portion of said re-configurable digital array is used for configuring said connected network, and
- the second portion of said re-configurable digital array is used to determine what type of said analog processing function is selected to be performed by said re-configurable analog array when formed in said connected network.
(canceled)
20-26. (canceled)
A system, the system comprising:
- an analog detector configured to output analog signals,
- one or more first processing elements configured to continuously perform mathematical operations on the signals outputted from the analog detector in response to instructions from a control unit,
- one or more second processing elements performing mathematical operations on the signals outputted from the analog detector in response to instructions from the control unit,
- one or more exchange registers performing signal conversion operations in response to instructions from a control unit, and
- control logic operatively connected to said one or more first processing elements and said one or more second processing elements, wherein the control logic is configured to control power delivered to said one or more first processing elements and said one or more second processing elements such that (i) the mathematical operations performed by said one or more first processing elements, (ii) the mathematical operations performed by said one or more second processing elements are performed in a particular sequence, and (iii) signal value conversions are performed in a particular sequence in order to process the analog signals outputted from the analog detector.
Dependencies are inferred from the claim text.