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US 2020/0403616 A1Published application
Computational memory cell and processing array device using complementary exclusive or memory cells
AssigneeGSI Technology, Inc.
InventorsLee-Lean SHU, Avidan AKERIB
Life of this patent
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Abstract
A memory cell and processing array that has a plurality of memory are capable of performing logic functions, including an exclusive OR (XOR) or an exclusive NOR (XNOR) logic function. The memory cell may have a read port in which the digital data stored in the storage cell of the memory cell is isolated from the read bit line.
Claims30
A memory computation cell, comprising:
- a storage cell having data and complementary data;
- two read bit lines connected to the storage cell that provide read access to the data and complementary data of the storage cell;
- an isolation circuit connected between the read bit lines and the storage cell that buffers the storage cell from a signal on either of the two read bit lines, the isolation circuit connected to a read word line and a complementary read word line;
- and
- wherein each read bit line is capable of performing a logic function when the memory cell is connected to the same read bit line with another memory cell and two logic functions are performed on the two read bit lines.
2 more elements
A processing array, comprising:
- a plurality of read bit lines;
- an array of memory cells having a plurality of rows of memory cells and a plurality of columns of memory cells, each memory cell having a storage cell, the read bit lines connecting to the columns of memory cells in the memory cell array;
- the array of memory cells having a first segment comprising at least two rows of memory cells and a second segment comprising one or a plurality of rows of memory cells, the first segment having each column of memory cells connected to at least two of the read bit lines and the second segment having each column of memory cells connected to at least one read bit line;
- a plurality of bit line read/write circuitry positioned between the first segment and the second segment in the array of memory cells, each bit line read/write circuitry having inputs from the at least two read bit lines of the first segment and an input from the at least one read bit line of the second segment;
- and
- wherein each read bit line connected to the memory cells in the first segment is capable of performing a logic function when at least one memory cell is connected to the same read bit line as another memory cell and two logic functions are performed on the two read bit lines in the first segment.
3 more elements
Dependencies are inferred from the claim text.