Semiconductor integrated circuit device
AssigneeSocionext Inc.
InventorKoshiro DATE
Life of this patent
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Abstract
A semiconductor integrated circuit device includes a flipflop circuit using vertical nanowire (VNW) FETs. A latch unit of the flipflop circuit includes: a feedback node; first p-type and n-type transistors each of which receives an input signal at one node and is connected to the feedback node at the other node; and second p-type and n-type transistors each connected to the feedback node at one node. In a standard cell, the tops of the first and second p-type and n-type transistors are connected to the feedback node.
Claims6
A semiconductor integrated circuit device comprising a standard cell configured to implement a flipflop circuit,
- wherein
- the flipflop circuit includes a latch unit,
- the latch unit includes
- a feedback node,
- a first p-type transistor and a first n-type transistor each of which receives an input signal at one node and is connected to the feedback node at the other node, and
- a second p-type transistor and a second n-type transistor each of which is connected to the feedback node at one node, and
- in the standard cell, the first and second p-type transistors and the first and second n-type transistors are vertical nanowire (VNW) FETs and are connected to the feedback node at their top electrodes.
A semiconductor integrated circuit device comprising a standard cell configured to implement a flipflop circuit,
- wherein
- the flipflop circuit includes a latch unit,
- the latch unit includes
- a first p-type transistor configured to receive a first clock at its gate electrode,
- a first n-type transistor configured to receive a second clock that is a reversed clock from the first clock, at its gate electrode,
- a second p-type transistor configured to receive the second clock at its gate electrode, and
- a second n-type transistor configured to receive the first clock at its gate electrode, and
- in the standard cell,
- the first and second p-type transistors and the first and second n-type transistors are vertical nanowire (VNW) FETs,
- the first p-type transistor and the second n-type transistor are placed at the same position in a first direction, and their gate electrodes are mutually connected by a first gate interconnect, and
- the first n-type transistor and the second p-type transistor are placed at the same position in the first direction, and their gate electrodes are mutually connected by a second gate interconnect.
A semiconductor integrated circuit device comprising a standard cell,
- wherein
- the standard cell includes
- first, second, and third transistors of a first conductivity type that are vertical nanowire (VNW) FETs, and
- a bottom region to which bottom electrodes of the first, second, and third transistors are connected in common, and
- top electrodes of the first, second, and third transistors are electrically isolated from one another.
Dependencies are inferred from the claim text.