Dc offset cancellation circuit and dc offset cancellation method

A DC offset cancellation circuit, comprising a high-speed amplifier, a voltage comparator, a microprocessor, and a digital-to-analog converter;

• the high-speed amplifier including an input stage with a DC offset cancellation function, an amplification stage, and an output buffer stage;
• the input stage having a first signal input terminal Inp, a second signal input terminal Inn, a first signal output terminal Outp, a second signal output terminal Outn, a first DC compensation terminal DCinp, and a second DC compensation terminal DCinn;
• the first signal input terminal Inp and the second signal input terminal Inn being configured to input input signals inp and inn, respectively;
• the first DC compensation terminal DCinp and the second DC compensation terminals DCinn being configured to input compensation signals dcinp and dcinn respectively, the first signal output terminal Outp and the second signal output terminal Outn being configured to output first output signals outp1 and outn1, respectively;
• the first output signals outp1 and outn1 being generated by the input stage after processing the input signals inp and inn and the compensation signals dcinp and dcinn;
• a non-inverting input terminal and an inverting input terminal of the amplification stage being connected to the first signal output terminal Outp and the second signal output terminal Outn, respectively;
• the amplification stage being configured to amplify the first output signals outp1 and outn1 to generate second output signals outp2 and outn2;
• a non-inverting input terminal and an inverting input terminal of the output buffer stage being connected to a non-inverting output terminal and an inverting output terminal of the amplification stage respectively, the output buffer stage being configured to buffer the second output signals outp2 and outn2 to generate output signals outp and outn;
• a non-inverting input terminal of the voltage comparator being connected to a non-inverting output terminal of the output buffer stage through a low-pass filter;
• an inverting input terminal of the voltage comparator being connected to an inverting output terminal of the output buffer stage through another low-pass filter;
• the two low-pass filters being configured to filter the output signals outp and outn of the output buffer stage to extract a pair of common-mode output signals G1 and G2 in the output signals outp and outn;
• the voltage comparator being configured to compare the common-mode output signals G1 and G2 and convert a comparison result into a digital logic signal DLS;
• the microprocessor being connected to an output terminal of the voltage comparator;
• the microprocessor being configured to receive the digital logic signal DLS and generate a digital control signal DCS according to the digital logic signal DLS;
• a digital signal input terminal Din of the digital-to-analog converter being connected to the microprocessor, a first analog signal output terminal Aoutp and a second analog signal output terminal Aoutn of the digital-to-analog converter being connected to the first DC compensation terminal DCinp and the second DC compensation terminal DCinn of the input stage respectively, the digital-to-analog converter being configured to receive the digital control signal DCS and generate the pair of compensation signals dcinp and dcinn according to the digital control signal DCS to be output to the first DC compensation terminal DCinp and the second DC compensation terminal DCinn of the input stage, respectively.