Adaptive sr turn-on control in an llc resonant converter

A power converter comprising, comprising:

• a primary side comprising:
• a primary winding of a transformer defining a first lead and a second lead;
• a parallel inductance connected between the first lead and the second lead of the primary winding of the transformer;
• a resonant inductor connected to the first lead of the primary winding of the transformer;
• a resonant capacitor;
• and
• a high-side field effect transistor (FET) configured to selectively conduct current from a power source to a switch node;
• and
• a secondary side comprising:
• a secondary winding of the transformer defining a third lead and a fourth lead;
• a synchronous rectification (SR) field effect transistor (FET) including a drain coupled to one of the third lead or the fourth lead of the transformer and defining a drain-source voltage;
• and
• a rectification controller coupled to the SR FET and configured to drive the SR FET to a conductive state in response to the drain-source voltage being less than an on-threshold voltage for an adaptive delay time;
• and
• wherein the rectification controller is configured to adjust the adaptive delay time using a time differential between first and second state transitions of a comparison between the drain-source voltage when the SR FET is non-conductive and an adaptive delay voltage.

An integrated circuit rectification controller comprising:

• a gate terminal, and a drain sense terminal having a drain-source voltage;
• a turn-on controller including a drain sense input coupled to the drain sense terminal and an on-delay output coupled to the gate terminal, the turn-on controller configured to energize the on-delay output in response to the drain-source voltage being less than an on-threshold voltage for an adaptive delay time;
• the turn-on controller including an adaptive delay comparator defining a comparator output and configured to assert the comparator output in response to the drain-source voltage being less than an adaptive delay voltage and to de-assert the comparator output in response to the drain-source voltage being greater than the adaptive delay voltage;
• and
• wherein the adaptive delay time is set based on a time between a first state transition of the comparator output of the adaptive delay comparator and a second state transition of the comparator output of the adaptive delay comparator when the gate output is de-asserted.

An integrated circuit rectification controller comprising:

• a gate terminal, and a drain sense terminal having a drain-source voltage;
• a turn-on controller including a drain sense input coupled to the drain sense terminal and an on-delay output coupled to the gate terminal, the turn-on controller configured to energize the on-delay output in response to the drain-source voltage being less than an on-threshold voltage for an adaptive delay time;
• the turn-on controller including an adaptive delay comparator defining a comparator output and configured to assert the comparator output in response to the drain-source voltage being less than an adaptive delay voltage and to de-assert the comparator output in response to the drain-source voltage being greater than the adaptive delay voltage;
• and
• wherein the adaptive delay time is set based on a time between a first state transition of the comparator output of the adaptive delay comparator and a second state transition of the comparator output of the adaptive delay comparator;
• a pre-on pulse generator including an enable input coupled to the comparator output of the adaptive delay comparator, and a pulse output, the pre-on pulse generator configured to assert the pulse output for a pulse duration in response to the comparator output of the adaptive delay comparator being asserted;
• an adaptive on-delay controller including a first input coupled to the pulse output of the pre-on pulse generator and a second input coupled to the comparator output of the adaptive delay comparator and an on-delay output, the adaptive on-delay controller comprising:
• a first counter having a first counter memory, the first counter configured to increment the first counter memory by a periodic clock signal after the first state transition of the SR FET drain-source voltage;
• a storage register having a storage memory and configured to store the value of the first counter memory as a stored value in the storage memory in response to the second state transition of the SR FET drain-source voltage;
• a second counter having a second counter memory, the second counter configured to increment the second counter memory by the periodic clock signal with the second input asserted;
• and
• a digital comparator configured to compare the value of the second counter memory with the stored value in the storage memory and to assert the on-delay output in response to the value of the second counter memory being greater than the stored value in the storage memory.

An integrated circuit rectification controller comprising:

• a gate terminal, and a drain sense terminal having a drain-source voltage
• a turn-on controller including a drain sense input coupled to the drain sense terminal and an on-delay output coupled to the gate terminal, the turn-on controller configured to energize the on-delay output in response to the drain-source voltage being less than an on-threshold voltage for an adaptive delay time;
• the turn-on controller including an adaptive delay comparator defining a comparator output and configured to assert the comparator output in response to the drain-source voltage being less than an adaptive delay voltage and to de-assert the comparator output in response to the drain-source voltage being greater than the adaptive delay voltage;
• and
• wherein the adaptive delay time is set based on a time between a first state transition of the comparator output of the adaptive delay comparator and a second state transition of the comparator output of the adaptive delay comparator;
• a current inversion detection block including a first input coupled to the drain sense terminal of the integrated circuit rectification controller, and a second input coupled to the gate terminal of the integrated circuit rectification controller, and a delay-enable output, the current inversion detection block configured to assert the delay-enable output in response to the first input having a voltage greater than a predetermined inversion detect voltage while the gate terminal of the integrated circuit rectification controller is asserted.

An integrated circuit rectification controller comprising:

• a gate terminal, and a drain sense terminal having a drain-source voltage;
• a turn-on controller including a drain sense input coupled to the drain sense terminal and an on-delay output coupled to the gate terminal, the turn-on controller configured to energize the on-delay output in response to the drain-source voltage being less than an on-threshold voltage for an adaptive delay time;
• the turn-on controller including an adaptive delay comparator defining a comparator output and configured to assert the comparator output in response to the drain-source voltage being less than an adaptive delay voltage and to de-assert the comparator output in response to the drain-source voltage being greater than the adaptive delay voltage;
• and
• wherein the adaptive delay time is set based on a time between a first state transition of the comparator output of the adaptive delay comparator and a second state transition of the comparator output of the adaptive delay comparator;
• a set-reset block including a set input and a reset input and a latching output, the set-reset block configured to assert the latching output in response to assertion of the set input and to de-assert the latching output in response to assertion of the reset input;
• and
• an off-threshold comparator including a non-inverting input connected to the drain sense terminal, and an inverting input having an off-threshold voltage, the off-threshold comparator configured to assert the reset input of the set-reset block in response to the drain-source voltage being greater than the off-threshold voltage on the inverting input.