US 2020/0403514 A1 · CONNECTION TERMINAL PATTERN AND LAYOUT FOR THREE-LEVEL BUCK REGULATOR

Abstract

Certain aspects of the present disclosure generally relate to a connection terminal pattern and layout for a three-level buck regulator. One example electronic module generally includes a substrate, an integrated circuit (IC) package disposed on the substrate and comprising transistors of a three-level buck regulator, a capacitive element of the three-level buck regulator disposed on the substrate, and an inductive element of the three-level buck regulator disposed on the substrate. In certain aspects, the capacitive element and the inductive element may be disposed adjacent to different sides of the IC package.

Claims22

Dependent claims

An electric module, comprising:

a substrate;
an integrated circuit (IC) package disposed on the substrate and comprising transistors of a three-level buck regulator;
a capacitive element of the three-level buck regulator disposed on the substrate;
and
an inductive element of the three-level buck regulator disposed on the substrate, the capacitive element and the inductive element being disposed adjacent to different sides of the IC package.

2 more elements

An integrated circuit (IC) package, comprising:

at least one first connection terminal for coupling to a first terminal of a capacitive element of a three-level buck regulator, the at least one first connection terminal being located at a first side of a terminal pattern of the IC package;
at least one second connection terminal coupled to a switching node of the three-level buck regulator, the at least one second connection terminal being located at a second side of the terminal pattern;
at least one third connection terminal for coupling to a second terminal of the capacitive element, the at least one third connection terminal being located at the first side of the terminal pattern;
and
an IC comprising:
a first transistor coupled between an input voltage (VIN) node and the at least one first connection terminal;
a second transistor coupled between the at least one first connection terminal and the at least one second connection terminal;
a third transistor coupled between the at least one second connection terminal and the at least one third connection terminal;
and
a fourth transistor coupled between the at least one third connection terminal and a reference potential node of the three-level buck regulator.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application

16/444,844Filed 18 Jun 2019

Published

24 Dec 2020

Term ends

Not estimatedThe source records don’t support an estimate.

Classification12 codes

H02M 3/156
Using semiconductor devices only: with automatic control of output voltage or current, e.g. switching regulators
G06F 1/3287
Power saving characterised by the action undertaken: by switching off individual functional units in the computer system
H02M 3/07
Using resistors or capacitors, e.g. potential divider: using capacitors charged and discharged alternately by semiconductor devices with control…
H02M 3/1582
Including plural semiconductor devices as final control devices for a single load: buck-boost converters

Connection terminal pattern and layout for three-level buck regulator

Life of this patent

Connection terminal pattern and layout for three-level buck regulator

Life of this patent

Abstract

Claims22