Magnetoresistive random access memory (mram) device

An MRAM device comprising:

• a lower electrode layer on a substrate;
• an MTJ structure on the lower electrode layer, the MTJ structure including:
• a fixed layer structure;
• a tunnel barrier structure on the fixed layer structure;
• a free layer on the tunnel barrier structure;
• and
• an upper oxide layer on the free layer;
• and
• an upper electrode layer on the MTJ structure,
• wherein the tunnel barrier structure has first and second tunnel barrier layers sequentially stacked, the first and second tunnel barrier layers including a first metal oxide and a second metal oxide, respectively, and the second tunnel barrier layer having a metal content less than a metal content of the first tunnel barrier layer, and
• wherein the upper oxide layer includes a third metal oxide.

An MRAM device comprising:

• a lower electrode layer on a substrate;
• an MTJ structure on the lower electrode layer, the MTJ structure including:
• a free layer;
• a tunnel barrier structure on the free layer;
• a fixed layer structure on the tunnel barrier structure;
• and
• an upper oxide layer on the fixed layer structure;
• and
• an upper electrode layer on the MTJ structure,
• wherein the tunnel barrier structure has first and second tunnel barrier layers sequentially stacked, the first and second tunnel barrier layers including a first metal oxide and a second metal oxide, respectively, and the second tunnel barrier layer having a metal content less than a metal content of the first tunnel barrier layer, and
• wherein the upper oxide layer includes a third metal oxide.

An MRAM device comprising:

• a gate electrode on a substrate;
• source/drain regions at upper portions, respectively, of the substrate adjacent to the gate electrode;
• a contact plug electrically connected to one of the source/drain regions;
• a lower electrode layer on the contact plug;
• an MTJ structure on the lower electrode layer, the MTJ structure including:
• a fixed layer structure;
• a tunnel barrier structure on the fixed layer structure;
• a free layer on the tunnel barrier structure;
• and
• an upper oxide layer on the free layer;
• an upper electrode layer on the MTJ structure;
• and
• a bit line on the upper electrode,
• wherein the tunnel barrier structure has first and second tunnel barrier layers sequentially stacked, the first and second tunnel barrier layers including a first metal oxide and a second metal oxide, respectively, and the second tunnel barrier layer having a metal content less than a metal content of the first tunnel barrier layer, and
• wherein the upper oxide layer includes a third metal oxide.