Transistors with uniform source/drain epitaxy

A semiconductor device, comprising:

• a plurality of stacked structures spaced apart from each other on a substrate, wherein the plurality of stacked structures each comprise a plurality of gate structures and a plurality of channel layers;
• and
• a plurality of epitaxial source/drain regions extending from the plurality of channel layers;
• wherein the plurality of epitaxial source/drain regions have the same or substantially the same height as each other.

A method for manufacturing a semiconductor device, comprising:

• forming a plurality of first semiconductor layers and a plurality of second semiconductor layers on a semiconductor substrate in a stacked configuration comprising a repeating arrangement of a second semiconductor layer stacked on a first semiconductor layer;
• forming a plurality of gate structures spaced apart from each other on the stacked configuration;
• patterning the stacked configuration into a plurality of patterned stacks spaced apart from each other, wherein the plurality of patterned stacks are under the plurality of gate structures;
• forming a plurality of sacrificial spacers on lateral sides of the plurality of gate structures;
• growing a plurality of source/drain regions from the plurality of second semiconductor layers, wherein the plurality of source/drain regions are adjacent the plurality of patterned stacks and include a plurality of pillar portions formed on lateral sides of the plurality of sacrificial spacers;
• selectively removing the plurality of sacrificial spacers;
• and
• removing the plurality of pillar portions.