Gate-sinking phemts having extremely uniform pinch-off/threshold voltage

A gate-sinking pHEMT, comprising:

• a compound semiconductor substrate;
• an epitaxial structure formed on the compound semiconductor substrate, wherein the epitaxial structure comprises:
• a buffer layer formed on the compound semiconductor substrate;
• a channel layer formed on the buffer layer;
• a Schottky layer formed on the channel layer, wherein the Schottky layer comprises from bottom to top at least two stacked regions of semiconductor material, wherein each of the two adjacent stacked regions differs in material from the other and provides a stacked region contact interface therebetween;
• a first contact layer formed on the Schottky layer, wherein the first contact layer is in contact with an upper surface of the topmost stacked region of the Schottky layer, and an uppermost contact interface is provided between the first contact layer and the topmost stacked region of the Schottky layer;
• and
• a first cap layer formed on the first contact layer;
• a source electrode formed on one end of the first cap layer;
• a drain electrode formed on the other end of the first cap layer, wherein a gate recess is located between the source electrode and the drain electrode;
• and
• a gate electrode, wherein the gate electrode comprises a first gate metal layer, wherein the first gate metal layer of the gate electrode is deposited on the first contact layer within the gate recess, wherein a gate-sinking region is beneath the first gate metal layer of the gate electrode, and wherein a bottom boundary of the gate-sinking region is located within 10 Å above or below the uppermost contact interface.