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US 2020/0403076 A1Published application
Thin film transistors with offset source and drain structures and process for forming such
AssigneeIntel Corporation
InventorsChieh-Jen KU, Pei-Hua WANG, Bernhard SELL, Travis W. LAJOIE
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Abstract
A device is disclosed. The device includes a source contact and a drain contact, a first dielectric between the source contact and the drain contact, a channel under the source contact and the drain contact, and a gate electrode below the channel, the gate electrode in an area under the first dielectric that does not laterally extend under the source contact or the drain contact. A second dielectric is above the gate electrode and underneath the channel.
Claims25
A device, comprising:
- a source contact and a drain contact;
- a first dielectric between the source contact and the drain contact;
- a channel under the source contact and the drain contact;
- a gate electrode below the channel, the gate electrode in an area under the first dielectric that does not laterally extend under the source contact or the drain contact;
- and
- a second dielectric above the gate electrode and underneath the channel.
3 more elements
A system, comprising:
- one or more processing components;
- and
- one or more data storage components, the data storage components including at least one device, the at least one device including:
- a source contact and a drain contact;
- a first dielectric between the source contact and the drain contact;
- a channel under the source contact and the drain contact;
- a gate electrode below the channel, the gate electrode occupying an area under the first dielectric that does not laterally extend under the source contact or the drain contact;
- and
- a second dielectric above the gate electrode and underneath the channel.
6 more elements
A method, comprising:
- forming etch stop material on an interconnect structure;
- patterning the etch stop material to form a plurality of vias;
- forming a gate conductor in the plurality vias to form a plurality of gate electrodes;
- forming a gate dielectric above the plurality of gate electrodes;
- forming channel material above the gate dielectric;
- forming a first interlayer dielectric above the channel material;
- forming a plurality of spaces in the interlayer dielectric, the channel material and the gate dielectric to define a plurality of active regions;
- forming a spacer material to line the plurality of spaces to define a plurality of isolation gaps;
- forming an isolation dielectric layer on the spacer material to fill the plurality of isolation gaps;
- forming a second interlayer dielectric layer above the plurality of filled isolation gaps;
- forming a plurality of source and drain contact spaces above the channel material wherein there is no lateral overlap of the plurality of gate electrodes and the plurality of source and drain contact spaces;
- and
- forming a plurality of source and drain contacts in the plurality of source and drain contact spaces.
10 more elements
A method, comprising:
- forming a source contact and a drain contact;
- forming a first dielectric between the source contact and the drain contact;
- forming a channel under the source contact and the drain contact;
- forming a gate electrode below the channel, the gate electrode in an area under the first dielectric that does not laterally extend under the source contact or the drain contact;
- and
- forming a second dielectric above the gate electrode and underneath the channel.
3 more elements
Dependencies are inferred from the claim text.