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US 2020/0403064 A1Published application
Field-effect transistor with size-reduced source/drain epitaxy and fabrication method thereof
AssigneePostech Research and Business Development Foundation
InventorsRock Hyun BAEK, Jun Sik YOON, Jin Su JEONG, Seung Hwan LEE
Life of this patent
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Abstract
Disclosed is a fin field-effect transistor having size-reduced source/drain regions so that a merging phenomenon of epitaxial structures between transistors in a layout is prevented, thus increasing the number of transistors per unit area, and so that an additional mask process is not required, thus maintain processing costs without change, and a method of manufacturing the same.
Claims12
A fin field-effect transistor comprising:
- a substrate;
- a channel formed in a predetermined region of the substrate;
- a gate formed in a predetermined region of the channel;
- source/drain regions formed at both sides of the channel along side surfaces of the channel on the substrate;
- and
- an insulating layer formed between the gate and the source/drain regions on an upper portion of the channel, so as to wrap the channel,
- wherein a maximum width ratio (W1/W2) of a width W2 of each of the source/drain regions to a width W1 of the channel is 1 based on a width direction (Y-axis direction, width) of the channel.
4 more elements
A method of manufacturing a fin field-effect transistor, comprising:
- (a) forming a channel, a gate, and an insulating layer in a predetermined region of a substrate so that the insulating layer is formed from both sides of the gate on an upper portion of the substrate;
- (b) performing etching along side surfaces of the channel and the insulating layer so as to etch even an upper portion of one side of the substrate through an etching process for forming source/drain regions, so that a designated region of the substrate and a region of the channel are exposed, and so that the insulating layer, patterned so as to wrap the exposed region of the substrate, is formed on the substrate;
- and
- (c) forming the source/drain regions, in which lateral growth of an epitaxial structure in a Y-axis direction is restricted through a selective epitaxial growth process, in the exposed region of the substrate and the channel,
- wherein the fin field-effect transistor is manufactured so that a maximum width ratio (W1/W2) of a width W2 of each of the source/drain regions to a width W1 of the channel is 1 based on a width direction (Y-axis direction, width) of the channel.
2 more elements
Dependencies are inferred from the claim text.