Mram integration with beol interconnect including top via

A method for reducing gouging of a dielectric cap by employing a subtractive etch technique forming a top via, the method comprising:

• forming a first conductive line with the top via in a logic area of a device;
• forming a conductive pad with a microstud in a memory area of the device;
• constructing MRAM pillars in the memory area, wherein the MRAM pillars are in direct contact with the microstud above the conductive pad;
• encapsulating the MRAM pillars with an encapsulation layer;
• recessing the encapsulation layer to expose an upper area of the MRAM pillars;
• and
• forming metal lines to a top section of the MRAM pillars and metal lines with vias to a top surface of the top via above the first conductive line.

A semiconductor structure for reducing gouging of a dielectric cap by employing a subtractive etch technique, the semiconductor structure comprising:

• a first conductive line with a top via in a logic area of a device;
• a conductive pad with a microstud in a memory area of the device;
• MRAM pillars constructed in the memory area, wherein the MRAM pillars are in direct contact with the microstud of the conductive pad;
• an encapsulation layer for encapsulating the MRAM pillars such that an upper area of the MRAM pillars is exposed;
• and
• a via extending from a top metal line connecting to an exposed upper area of the MRAM pillars and vias extending from top metal lines to a top surface of the first conductive line.