Memory device and manufacturing method thereof

A manufacturing method of a memory device, comprising:

• forming a first signal line on a substrate;
• forming a charge trap transistor on the first signal line, wherein the charge trap transistor comprises a channel pillar standing on the first signal line, a gate pattern laterally surrounding the channel pillar, two dielectric patterns laterally surrounding the channel pillar and lying above and under the gate pattern, and a charge storage layer lining between the gate pattern and the channel pillar and lining between the gate pattern and the two dielectric patterns;
• forming a second signal line on the charge trap transistor;
• and
• performing formation of the charge trap transistor one more time, such that the channel pillars of the charge trap transistors are vertically separated from each other by the second signal line.

A manufacturing method of a memory device, comprising:

• forming first signal lines on a substrate, wherein the first signal lines are laterally spaced apart from one another, and extend along the same direction;
• performing a process cycle comprising:
• forming stack structures on the substrate, wherein the first signal lines are intersected and covered by the stack structures, the stack structures are laterally spaced apart from one another by spacings, and the stack structures respectively comprise two dielectric layers and a sacrifice layer sandwiched by the two dielectric layers;
• forming through holes in each of the stack structures, wherein the through holes penetrate through the stack structures along a stacking direction of the stack structures;
• filling a semiconductor material into the through holes to form channel pillars;
• replacing each of the sacrifice layers with a charge storage layer and a gate pattern;
• forming isolation structures in the spacings;
• and
• forming second signal lines on upper ones of the dielectric layers and the isolation structures;
• and
• repeating the process cycle multiple times.