Vertical memory devices

A vertical memory device, comprising:

• gate electrodes disposed on a substrate and spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate;
• a channel extending in the vertical direction, and positioned adjacent to the gate electrodes, the channel including a protrusion portion that protrudes in a horizontal direction substantially parallel to the upper surface of the substrate toward each of the gate electrodes;
• a tunnel insulation pattern disposed on a portion of an outer sidewall of the channel adjacent to each of the gate electrodes and the protrusion portion of the channel in the horizontal direction;
• charge trapping pattern structures disposed between the tunnel insulation pattern and each of the gate electrodes, each of the charge trapping pattern structures including upper and lower charge trapping patterns spaced apart from each other in the vertical direction;
• and
• blocking pattern structures disposed between the charge trapping patterns and each of the gate electrodes,
• wherein a sidewall of each of the gate electrodes adjacent to the channel is concave along the horizontal direction.

A vertical memory device, comprising:

• gate electrodes disposed on a substrate and spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate;
• a channel extending in the vertical direction and positioned adjacent to the gate electrodes, the channel having recesses formed on portions of an outer sidewall of the channel adjacent to each of the gate electrodes, the recesses spaced apart from each other in the vertical direction;
• a tunnel insulation pattern filling each of the recesses, and protruding toward each of the gate electrodes in a horizontal direction substantially parallel to the upper surface of the substrate;
• charge trapping pattern structures disposed between the tunnel insulation pattern and each of the gate electrodes, each of the charge trapping pattern structures including upper and lower charge trapping patterns spaced apart from each other in the vertical direction;
• and
• blocking pattern structures disposed between the charge trapping patterns and each of the gate electrodes.