Three-dimensional flash memory device including channel structures having enlarged portions

A three-dimensional flash memory device having a cell area and an extension area, the device comprising:

• a substrate;
• a lower word line stack and an upper word line stack on the substrate;
• an interlayer dielectric layer between the lower word line stack and the upper word line stack;
• a cell channel structure in the cell area;
• and
• a dummy channel structure in the extension area,
• wherein the cell channel structure includes:
• a lower cell channel structure penetrating the lower word line stack and connected to the substrate;
• an upper cell channel structure penetrating the upper word line stack;
• and
• a cell channel enlarged portion between the lower cell channel structure and the upper cell channel structure,
• wherein the dummy channel structure includes:
• a lower dummy channel structure penetrating the lower word line stack and connected to the substrate;
• an upper dummy channel structure penetrating the upper word line stack;
• and
• a dummy channel enlarged portion between the lower dummy channel structure and the upper dummy channel structure,
• wherein a bottom surface of the dummy channel enlarged portion is at a lower level than a bottom surface of the interlayer dielectric layer.

A three-dimensional flash memory device having a cell area and an extension area, the device comprising:

• a substrate;
• a lower word line stack on the substrate and including a plurality of stacked lower word lines,
• an upper word line stack on the substrate and including a plurality of stacked upper word lines;
• an interlayer dielectric layer between the lower word line stack and the upper word line stack;
• a cell channel structure in the cell area;
• and
• a dummy channel structure and a vertical contact structure in the extension area,
• wherein:
• the cell channel structure includes:
• a lower cell channel structure penetrating the lower word line stack and connected to the substrate;
• an upper cell channel structure penetrating the upper word line stack;
• and
• a cell channel enlarged portion between the lower cell channel structure and the upper cell channel structure,
• the dummy channel structure includes:
• a lower dummy channel structure penetrating the lower word line stack and connected to the substrate;
• an upper dummy channel structure penetrating the upper word line stack;
• and
• a dummy channel enlarged portion between the lower dummy channel structure and the upper dummy channel structure,
• the vertical contact structure is connected to one lower word line of the lower word line stack or one upper word line of the upper word line stack,
• a horizontal width of the lower dummy channel structure is greater than a horizontal width of the lower cell channel structure,
• a horizontal width of the dummy channel enlarged portion is greater than a horizontal width of the cell channel enlarged portion,
• a bottom surface of the dummy channel enlarged portion is at a lower level than a bottom surface of the interlayer dielectric layer, and
• side surfaces of the dummy channel enlarged portion and side surfaces of the cell channel enlarged portion are rounded.