Semiconductor device
AssigneeRenesas Electronics Corporation
InventorYoshiyuki KAWASHIMA
Life of this patent
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Abstract
Fins lined up in a Y direction, a control gate electrode and a memory gate electrode each extending in the Y direction so as to straddle the fins, a plurality of first plugs electrically connected with a drain region formed in each of the fins, and a plurality of second plugs electrically connected with a source region formed in each of the fins are formed. Here, a N-th plug of the plurality of first plugs lined up in the Y direction is coupled with each of (2N−1)-th and 2N-th fins in the Y direction. Also, a N-th plug of the plurality of second plugs lined up in the Y direction is coupled with each of 2N-th and (2N+1)-th fins in the Y direction.
Claims7
A semiconductor device comprising:
- a semiconductor substrate;
- a plurality of first protruding portions each protruded from an upper surface of the semiconductor substrate and each extended in a first direction along the upper surface of the semiconductor substrate, each of the plurality of first protruding portions being a part of the semiconductor substrate;
- a first gate electrode formed on each of an upper surface of each of the plurality of first protruding portions and a side surface of each of the plurality of first protruding portions via a first insulating film, and extended in a second direction crossing to the first direction;
- a second gate electrode formed on each of the upper surface of each of the plurality of first protruding portions and the side surface of each of the plurality of first protruding portions via a second insulating film, which is a charge storage portion, and extended in the second direction, the second gate electrode being adjacent to one of side surfaces of the first gate electrode via an insulating film;
- a first semiconductor region formed in each of the plurality of first protruding portions so as to arranged next to the first gate electrode in plan view;
- a second semiconductor region formed in each of the plurality of first protruding portions so as to arranged next to the second gate electrode in plan view;
- a plurality of first plugs formed on the plurality of first protruding portions, respectively, and lined up in the second direction;
- and
- a plurality of second plugs formed on the plurality of first protruding portions, respectively, and lined up in the second direction,
- wherein the first gate electrode, the second gate electrode, the first semiconductor region and the second semiconductor region compose a non-volatile storage element,
- wherein a N-th plug of the plurality of first plugs lined up in the second direction is electrically connected with the first semiconductor region formed in each of a (2N−1)-th protruding portion of the plurality of first protruding portions and a 2N-th protruding portion of the plurality of first protruding portions, which are lined up in the second direction, and
- wherein a N-th plug of the plurality of second plugs lined up in the second direction is electrically connected with the second semiconductor region formed in each of a 2N-th protruding portion of the plurality of first protruding portions and a (2N+1)-th protruding portion of the plurality of first protruding portions, which are lined up in the second direction.
Dependencies are inferred from the claim text.