Flash and Method for Manufacturing the Same

A method for manufacturing a flash, wherein the flash comprises a plurality of memory cells, and the steps of forming the memory cells comprise:

• step 1:
• providing a semiconductor substrate and forming a first shallow trench in the surface area of the semiconductor substrate in the forming area of a channel region;
• step 2:
• forming a hard mask layer, the hard mask layer fully filling the first shallow trench and covering the surface of the semiconductor substrate outside the first shallow trench;
• step 3:
• using a photolithography process to define the formation area of the second shallow trench, and the hard mask layer and the first semiconductor substrate are sequentially etched to form the second shallow trench according to the photolithographic definition;
• step 4:
• filling a shallow trench field oxide into the second shallow trench, and performing flattening to enable the surface of the shallow trench field oxide to be in flush with the surface of the hard mask layer, the shallow trench field oxide defining an active region;
• step 5:
• removing the hard mask layer in a self-aligned manner by using the shallow trench field oxide as a mask, and sequentially forming a tunneling dielectric layer and a polysilicon floating gate in the removed area of the hard mask layer, the two side surfaces in the width direction of the polysilicon floating gate and the two side surfaces in the width direction of the active region being self-aligned;
• step 6:
• etching back the shallow trench field oxide in a self-aligned manner by using the polysilicon floating gate as a mask, and etching back the surface of the shallow trench field oxide to be in flush with the surface of the semiconductor substrate;
• step 7:
• forming a control dielectric layer, the control dielectric layer covering the top surface and side surfaces of the polysilicon floating gate;
• step 8:
• forming a polysilicon control gate on the surface of the control dielectric layer;
• step 9:
• using a photolithography process to define the formation area of a gate structure, and sequentially etching the polysilicon control gate, the control dielectric layer and the polysilicon floating gate according to the photolithographic definition to form the gate structure, the side surfaces of the polysilicon floating gate formed by etching being the two side surfaces in the length direction;
• the gate structure of each memory cell being formed by superposing the corresponding tunneling dielectric layer, the polysilicon floating gate, the control dielectric layer and the polysilicon control gate;
• step 10:
• forming a source region and a drain region in a self-aligned manner in the active regions on the two sides in the length direction of the polysilicon floating gate of the gate structure;
• the channel region is located in the surface area of the semiconductor substrate covered by the polysilicon floating gate between the source region and the drain region;
• the surface of the channel region covered by the polysilicon floating gate is used to form a channel connecting the source region and the drain region, the channel is provided with a longitudinal structure extending along the side surface of the first shallow trench, and the longitudinal structure of the channel enables the length of the channel to be increased and enables the length of the polysilicon floating gate to be decreased under the condition that the length of the channel satisfies a short channel effect, thus reducing the area of the memory cell.