Stacked-nanosheet semiconductor structures
AssigneeInternational Business Machines Corporation
InventorsAlexander Reznicek, Bahman Hekmatshoartabari, Karthik Balakrishnan, Jeng-Bang Yau
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Abstract
Semiconductor structures and methods of making the same. The semiconductor structures including at least two vertically stacked nanosheet devices. In one embodiment, an integrated circuit includes a plurality of horizontal nanosheet devices (HNS devices) that are stacked vertically, on top of each other, relative to a top surface of a substrate. The plurality of HNS devices including a first HNS device and a second HNS device that each have source and drain structures.
Claims19
A semiconductor structure that includes an erasable programmable read-only memory (EPROM) bit cell, the EPROM bit cell comprising:
- a stacked pair of field-effect transistors including a first field-effect transistor (FET) and a second FET, the first FET having a first gate terminal connected to a word-line and a first source/drain terminal connected to a select-line;
- wherein:
- the first and second FET are horizontal nano-sheet FETs (HNS-FETs).
(canceled)
(canceled)
A semiconductor structure including an erasable programmable read-only inverter, the erasable programmable read-only inverter comprising:
- a stacked pair of field-effect transistors including a first field-effect transistor (FET) and a second FET, the first FET having a first gate terminal connected to an input line and a first source/drain terminal connected to a first power supply line;
- wherein:
- the first and second FET are horizontal nano-sheet FETs (HNS-FETs).
14-15. (canceled)
The erasable programmable read-only inverter of claim 14, wherein a second source/drain terminal of the first FET is connected to both of (i) a first source/drain terminal of the second FET and (ii) an output line.
Dependencies are inferred from the claim text.