Tie off device

A semiconductor device, comprising:

• a first power rail;
• a second power rail;
• a first fin extending in a first direction;
• a first PMOS transistor including the first fin and a first gate, the first PMOS transistor having a first threshold voltage (VT), the first gate extending in a second direction perpendicular to the first direction;
• a second PMOS transistor including the first fin and a second gate extending in the second direction, the second PMOS transistor having a second VT different than the first VT, and wherein the second gate is connected to the first power rail;
• a second fin extending in the first direction;
• a first NMOS transistor including the second fin and the first gate, the first NMOS transistor having the first VT;
• a second NMOS transistor including the second fin and the second gate, the second NMOS transistor having the second VT, and wherein the second gate is connected to the second power rail.

A method, comprising:

• forming a first active area on a substrate, the first active area including a first threshold voltage (VT) region and a second VT region;
• forming a first gate contacting the first VT region of the first active area to form a first transistor having a first VT;
• forming a second gate contacting the second VT region of the first active area to form a second transistor having a second VT different than the first VT;
• forming a third gate contacting the first active area between the first gate and the second gate to form a tie-off transistor positioned between the first transistor and the second transistor;
• and
• connecting the third gate to a power rail to maintain the tie-off transistor in an off state.