Methods, apparatus and system for forming on-chip metal-insulator-meal (mim) capacitor

A semiconductor device, comprising:

• a semiconductor substrate;
• an isolation feature on the substrate;
• a plurality of gates on the isolation feature, wherein each gate comprises a gate electrode and a high-k dielectric layer disposed between the gate electrode and the isolation feature and disposed on and in contact with at least one side of the gate electrode;
• and
• a fill metal between the plurality of gates on the isolation feature.

A semiconductor device, comprising:

• a semiconductor substrate;
• a fin on an active region of the semiconductor substrate;
• an isolation feature on the substrate;
• a plurality of gates on the isolation feature, wherein each gate comprises a gate electrode and a high-k dielectric layer disposed between the gate electrode and the isolation feature and touching at least one side of the gate electrode, wherein at least one gate of the plurality of gates is on the fin;
• a spacer touching the high-k dielectric layer on at least one side of the gate electrode of the at least one gate on the fin and touching the high-k dielectric layer on at least one side of each gate electrode of the plurality of gates on the isolation feature;
• and
• a fill metal between the plurality of gates on the isolation feature, wherein the fill metal after deposition touches the high-k dielectric layer on at least one side of and below a top of the gate electrode of at least one of the plurality of gates.

A semiconductor device, comprising:

• a semiconductor substrate;
• an isolation feature on the substrate;
• and
• a plurality of capacitors on the isolation feature, wherein each capacitor comprises:
• a first plurality of gates, wherein each gate comprises a gate electrode, a high-k dielectric layer disposed between the gate electrode and the isolation feature and touching at least one side of the gate electrode, and a nitride cap on the gate electrode and the high-k dielectric layer;
• a fill metal between the plurality of gates on the isolation feature, wherein the fill metal touches the high-k dielectric layer on at least one side of and below a top of the gate electrode of at least one of the first plurality of gates;
• and
• a capacitor dielectric between the high-k dielectric layer on each side of each gate of the first plurality of gates on the isolation feature and the fill metal between the first plurality of gates.