Stacked semiconductor package having an interposer

A stacked semiconductor package comprising:

• a package substrate;
• a lower chip, an interposer, and an upper chip sequentially stacked on the package substrate;
• and
• bonding wires electrically connecting the package substrate and the interposer,
• wherein the interposer comprises:
• lower chip connection pads disposed on a lower surface of the interposer, wherein the lower chip connection pads are electrically connected to the lower chip;
• first upper chip connection pads and second upper chip connection pads disposed on an upper surface of the interposer, wherein the first upper chip connection pads and the second upper chip connection pads are electrically connected to the upper chip;
• wire bonding pads disposed on the upper surface of the interposer and bonded to the bonding wires;
• first redistribution lines disposed on the upper surface of the interposer, the first redistribution lines electrically connecting the second upper chip connection pads to the wire bonding pads;
• and
• through via electrodes electrically connecting the lower chip connection pads to the first upper chip connection pads.