Semiconductor packages having improved thermal discharge and electromagnetic shielding characteristics

A semiconductor package, comprising:

• a wiring substrate;
• an interposer chip disposed on the wiring substrate;
• a first memory chip disposed on the interposer chip, wherein the first memory chip is electrically connected to the wiring substrate;
• a second memory chip disposed on the interposer chip, wherein the second memory chip isolated from direct contact with first memory chip, and the second memory chip is electrically connected to the wiring substrate;
• a mold layer formed on the wiring substrate, wherein the mold layer covers the first memory chip and the second memory chip, and wherein the mold layer comprises a mold via hole or a mold trench;
• an electromagnetic shielding layer formed on surfaces of the mold layer and a surface of a portion of the interposer chip;
• and
• a thermal discharge layer disposed on the electromagnetic shielding layer within the mold via hole or the mold trench,
• wherein the first memory chip includes a first multilayer chip that includes a plurality of first sub-chips which are stacked on the interposer chip,
• wherein the plurality of first sub-chips are electrically connected to each other through one or more through-vias,
• wherein the second memory chip includes a second multilayer chip that includes a plurality of second sub-chips which are stacked on the interposer chip,
• wherein the plurality of second sub-chips are electrically connected to each other through one or more through-vias, and
• wherein the electromagnetic shielding layer is directly in contact with the portion of the interposer chip at a bottom of the mod via hole or the mold trench.

A semiconductor package, comprising:

• a wiring substrate;
• an interposer chip disposed on the wiring substrate;
• a first memory chip disposed on the interposer chip, wherein the first memory chip is electrically connected to the wiring substrate;
• a second memory chip disposed on the interposer chip, wherein the second memory chip is isolated from direct contact with the first memory chip, and the second memory chip is electrically connected to the wiring substrate;
• a mold layer formed on the wiring substrate, the mold layer covers the first memory chip and the second memory chip, and wherein the mold layer comprises a plurality of mold via holes or mold trenches in both a center region between the first memory chip and the second memory chip and in an edge portion of the interposer chip;
• an electromagnetic shielding layer formed on the surfaces of the mold layer and a surface of a portion of the interposer chip;
• and
• a thermal discharge layer disposed on the electromagnetic shielding layer within the plurality of mold via holes or mold trenches,
• wherein each memory chip of the first memory chip and the second memory chip includes a separate multilayer chip, each separate multilayer chip including a separate plurality of sub-chips which are stacked,
• wherein the separate plurality of sub-chips are electrically connected to each other through one or more through-vias,
• wherein the electromagnetic shielding layer is directly in contact with the portion of the interposer chip at a bottom of the plurality of mold via holes or mold trenches, and
• wherein the first memory chip and the second memory chip are each electrically connected to the wiring substrate via a separate bonding wire and via the interposer chip.