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US 2020/0402928 A1Published application
Integrated circuit containing a decoy structure
AssigneeSTMicroelectronics (Rousset) SAS
InventorsJulien DELALLEAU, Christian RIVERO
Life of this patent
Estimating the term…
Abstract
An integrated circuit includes a substrate, an interconnection part, and an isolating region located between the substrate and the interconnection part. A decoy structure is located within the isolating region and includes a silicided sector which is electrically isolated from the substrate.
Claims18
An integrated circuit, comprising:
- a substrate having an upper face and comprising a substrate area;
- an interconnection part;
- an isolating region located between the substrate and the interconnection part and covering the substrate area;
- a gate region having a central area and a tab, said tab having a silicided part forming a silicided sector projecting from the central area, parallel to the upper face of the substrate area, towards a silicided portion of the substrate area;
- an isolating layer electrically isolating the gate region, the tab and the silicided sector from the upper face of substrate and the substrate area;
- and
- a decoy structure located above the substrate area and within said isolating region, said decoy structure comprising:
- a first electrically conductive contact passing through said isolating region, having a first end simultaneously in electrical and physical contact with said silicided sector and said silicided portion of said substrate area, and a second end electrically coupled to said interconnection part.
5 more elements
An integrated circuit, comprising:
- a transistor active region of a semiconductor substrate region delimited by an insulating region;
- a source region of a transistor within the transistor active region;
- a polysilicon gate region for the transistor;
- and
- a source contact to the source region, wherein the source contact comprises:
- a lateral tab extending from the polysilicon gate region over the source region but which is insulated from the source region by an insulating layer, and wherein said lateral tab includes a first silicide portion;
- a second silicide portion within the source region;
- and
- an electrical contact passing through a dielectric layer to make electrical and physical contact with both the first silicide portion and the second silicide portion and thus electrically connect the polysilicon gate region to the source region.
6 more elements
Dependencies are inferred from the claim text.