Vertical memory devices

A vertical memory device, comprising:

• a circuit pattern on a first substrate, the first substrate including a cell region and a peripheral circuit region adjacent to the cell region;
• a first insulating interlayer on the first substrate, the first insulating interlayer covering the circuit pattern;
• a first bending prevention layer on the first insulating interlayer on the cell region and the peripheral circuit region;
• a second substrate on the first bending prevention layer on the cell region;
• gate electrodes spaced apart from each other in a first direction on the second substrate on the cell region, the first direction substantially perpendicular to an upper surface of the first substrate;
• a channel extending through the gate electrodes in the first direction on the cell region;
• and
• a first contact plug extending in the first direction through the first bending prevention layer on the peripheral circuit region, the first contact plug being electrically connected to the circuit pattern.

A vertical memory device, comprising:

• transistors on a first substrate;
• lower wirings on the first substrate, the lower wirings being electrically connected to the transistors;
• a first insulating interlayer on the first substrate, the first insulating interlayer covering the transistors and the lower wirings;
• a bending prevention layer on the first insulating interlayer, the bending prevention layer extending in a first direction substantially parallel to an upper surface of the first substrate;
• a second substrate on the bending prevention layer;
• gate electrodes spaced apart from each other in a second direction on the second substrate, the second direction being substantially perpendicular to the upper surface of the first substrate;
• a second insulating interlayer on the second substrate, the second insulating interlayer covering sidewalls of the gate electrodes;
• channels extending through the gate electrodes in the second direction;
• upper wirings on the gate electrodes, the upper wirings being electrically connected to the gate electrodes;
• a first contact plug structure extending through the gate electrodes, the second substrate and the bending prevention layer, the first contact plug structure being electrically connected to a first lower wiring of the lower wirings;
• and
• a second contact plug extending through the second insulating interlayer and the bending prevention layer, the second contact plug being electrically connected to a second lower wiring of the lower wirings.