Monolithic 3D Integration Inter-Tier Vias Insertion Scheme and Associated Layout Structure

A method, comprising:

• receiving a layout design for an Integrated Circuit (IC) cell;
• decomposing the layout design into a first segment of the IC cell and a second segment of the IC cell;
• and
• fabricating an IC device that includes a top portion and a bottom portion that is vertically stacked below the top portion, wherein the first segment of the IC cell is fabricated on the top portion, and wherein the second segment of the IC cell is fabricated on the bottom portion, and wherein the fabricating includes fabricating a plurality of vias that electrically connect the top portion with the bottom portion.

An apparatus, comprising:

• a first tier device that includes a plurality of first transistors and a plurality of first metal lines;
• a second tier device that includes a plurality of second transistors and a plurality of second metal lines;
• and
• a plurality of inter-tier vias (ITVs) that are each electrically coupled to both a respective one of the first metal lines and a respective one of the second metal lines;
• wherein the first tier device is disposed over the second tier device.