Memory Arrays And Methods Used In Forming A Memory Array And Conductive Through-Array-Vias (TAVs)

A method used in forming a memory array and conductive through-array-vias (TAVs), comprising:

• forming a stack comprising an uppermost conductor tier and vertically-alternating insulative tiers and wordline tiers, the uppermost conductor tier and wordline tiers comprising a first material, the insulative tiers comprising a second material of different composition from that of the first material;
• forming channel-material strings through the insulative tiers and the wordline tiers;
• forming a mask comprising horizontally-elongated trench openings and operative TAV openings above the stack;
• etching unmasked portions of the stack through the trench and operative TAV openings in the mask to form horizontally-elongated trench openings in the stack and to form operative TAV openings in the stack;
• forming conductive material in the operative TAV openings in the stack to form individual operative TAVs in individual of the operative TAV openings in the stack;
• removing the first material after forming the conductive material in the operative TAV openings in the stack to form wordline-tier voids and an uppermost-conductor-tier void;
• forming conducting material in the wordline-tier voids to comprise individual wordlines and in the uppermost-conductor-tier void;
• and
• after forming the conducting material, forming a wordline-intervening structure in individual of the trench openings in the stack.

A memory array comprising:

• a vertical stack comprising an uppermost insulating tier, an uppermost conductor tier below the insulating tier, and alternating insulative tiers and wordline tiers below the uppermost conductor tier, the wordline tiers comprising gate regions of individual memory cells, the gate regions individually comprising part of a wordline in individual of the wordline tiers;
• channel-material strings extending elevationally through the insulative tiers and the wordline tiers;
• the individual memory cells comprising a memory structure laterally between individual of the gate regions and channel material of the channel-material strings;
• a wordline-intervening structure extending through the stack between immediately-adjacent of the wordlines;
• and
• a step atop or above an uppermost of the insulative tiers of the alternating insulative tiers and wordline tiers on at least one side of individual of the wordlines, the wordline-intervening structure being atop the step.

A memory array comprising:

• a vertical stack comprising an uppermost insulating tier, an uppermost conductor tier below the insulating tier, and alternating insulative tiers and wordline tiers below the uppermost conductor tier, the wordline tiers comprising gate regions of individual memory cells, the gate regions individually comprising part of a wordline in individual of the wordline tiers;
• channel-material strings extending elevationally through the insulative tiers and the wordline tiers;
• the individual memory cells comprising a memory structure laterally between individual of the gate region and channel material of the channel-material strings;
• a wordline-intervening structure extending through the stack between immediately-adjacent of the wordlines;
• and
• the wordline-intervening structure comprising opposing laterally-outer longitudinal edges, at least some of each of the opposing laterally-outer longitudinal edges above the uppermost conductor tier being less overall steep than the opposing laterally-outer longitudinal edges below the uppermost conductor tier.