Semiconductor Device and Method to Minimize Stress on Stack Via

A method of making a semiconductor device, comprising:

• providing a semiconductor die;
• disposing a first insulating layer over the semiconductor die;
• forming a first via in the first insulating layer over a contact pad of the semiconductor die;
• disposing a first conductive layer over the first insulating layer and into the first via;
• disposing a second insulating layer over the first insulating layer and first conductive layer;
• and
• forming a second via in the second insulating layer over the first conductive layer and aligned with the first via.

A semiconductor device, comprising:

• a semiconductor die;
• a first insulating layer disposed over the semiconductor die;
• a via formed in the first insulating layer over a contact pad of the semiconductor die;
• a first conductive layer disposed over the first insulating layer and in the via;
• a second insulating layer disposed over a portion of the first insulating layer and first conductive layer;
• and
• an opening formed through the second insulating layer to leave an island of the second insulating layer over a portion of the first conductive layer.

A semiconductor device, comprising:

• a semiconductor die;
• a first insulating layer disposed over the semiconductor die;
• a first via formed in the first insulating layer over a contact pad of the semiconductor die;
• a first conductive layer disposed over the first insulating layer and in the first via;
• a second insulating layer disposed over the first insulating layer and first conductive layer;
• a second via formed in the second insulating layer over the first conductive layer and the first via;
• and
• a second conductive layer disposed over the first conductive layer and second insulating layer with an opening in the second conductive layer extending across the first via.