Semiconductor chamber coatings and processes

A method for coating a component of a semiconductor processing chamber, the method comprising:

• positioning a component having an exposed surface within a chamber;
• depositing a conformal layer about the exposed surface of the component, wherein the conformal layer is characterized by an exposed surface opposite a surface in contact with the component;
• preparing the exposed surface of the conformal layer, wherein preparing the exposed surface of the conformal layer comprises:
• flowing an argon-containing precursor into a processing region of the semiconductor processing chamber,
• forming a plasma from the argon-containing precursor to produce plasma effluents, and
• contacting the surface of the conformal layer with the plasma effluents;
• and
• depositing a non-metal oxide layer over the surface of the conformal layer, wherein the non-metal oxide layer is characterized by an amorphous microstructure.

An etching method, the method comprising:

• flowing a fluorine-containing etchant into a semiconductor processing chamber, wherein the semiconductor process chamber is maintained at a temperature less than or about 0° C. with a relative humidity of greater than or about 10% to 90%;
• etching a substrate positioned on a pedestal within the semiconductor processing chamber with the fluorine-containing etchant;
• contacting the pedestal with the fluorine-containing etchant, wherein the pedestal comprises a corrosion resistant coating, wherein the corrosion resistant coating comprises:
• a conformal layer which extends about the pedestal, wherein the conformal layer comprises a surface characterized by a surface roughness of from about 29 Sa to about 30 Sa, and
• a non-metal oxide layer which extends over the surface of the conformal layer, wherein the non-metal oxide layer is characterized by an amorphous microstructure having a hardness of from about 300 HV to about 10,000 HV, and wherein the non-metal oxide layer is characterized by a sp2 to sp3 hybridization ratio of from about 0.01 to about 0.5 and a hydrogen content of from about 1 wt. % to about 35 wt. %;
• andwherein wafer-level particle contribution from the pedestal is maintained at less than or about 0.01 ppm for nickel and less than or about 0.01 ppm for aluminum during the etching.