Two-Layer Code with Low Parity Cost for Memory Sub-Systems
AssigneeMicron Technology, Inc.
InventorsSanjay Subbarao, James Fitzpatrick
Life of this patent
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AssigneeMicron Technology, Inc.
InventorsSanjay Subbarao, James Fitzpatrick
Estimating the term…
A memory sub-system configured to encode data using an error correcting code and an erasure code for storing data into memory cells and to decode data retrieved from the memory cells. For example, the data units of a predetermined size are separately encoded using the error correcting code (e.g., a low-density parity-check (LDPC) code) to generate parity data of a first layer. Symbols within the data units are cross encoded using the erasure code. Parity symbols of a second layer are calculated according to the erasure code. A collection of parity symbols having a total size equal to the predetermined size can be further encoded using the error correcting code to generate parity data for the parity symbols.
A method, comprising:
A non-transitory computer storage medium storing instructions which, when executed in a memory sub-system, causes the memory sub-system to perform a method, the method comprising:
A memory sub-system, comprising:
Dependencies are inferred from the claim text.