US 2020/0402603 A1 · SEMICONDUCTOR DEVICE AND TEST METHOD THEREOF

Abstract

A semiconductor device includes an internal power supply generation circuit that generates an internal power supply voltage from an external power supply voltage and a non-volatile memory circuit. The semiconductor device sets the internal power supply voltage generated by the internal power supply generation circuit based on data stored in the non-volatile memory circuit. A mode signal that switches the internal power supply voltage is set in the non-volatile memory circuit. The mode signal is set to a burn-in mode before a burn-in test and is set to a normal mode after the burn-in test. In the burn-in test, when a VCC burn-in voltage is applied to a VCC terminal to start the semiconductor device, the internal power supply generation circuit generates a VDD burn-in voltage upon receiving the mode signal set in the burn-in mode.

Claims17

Dependent claims

A semiconductor device having an external power supply terminal, the semiconductor device comprising:

an internal power supply generation circuit configured to generate an internal power supply voltage from the external power supply voltage applied to an external power supply terminal;
and
a non-volatile memory circuit configured to store therein data rewritable externally,
wherein the internal power supply generation circuit sets the internal power supply voltage based on the data stored in the non-volatile memory circuit.

1 more element

A test method of a semiconductor device including an internal power supply generation circuit configured to generate an internal power supply voltage from an external power supply voltage applied to an external power supply terminal, a non-volatile memory circuit configured to store therein data rewritable externally, and a control circuit configured to operate based on data stored in the non-volatile memory circuit in response to external power supply voltage being applied to start the semiconductor device, the test method comprising:

writing, by a characteristics test apparatus, data corresponding to a burn-in mode in the non-volatile memory circuit;
reading, by a burn-in test apparatus, the data stored in the non-volatile memory circuit in response to a first burn-in voltage being applied to the external power supply terminal to start the semiconductor device, causing, by the burn-in test apparatus, the internal power supply generation circuit to generate a second burn-in voltage in accordance with the data, and performing, by the burn-in test apparatus, a burn-in test on the semiconductor device with the first burn-in voltage and the second burn-in voltage;
and
rewriting, by the characteristics test apparatus, the data in the non-volatile memory circuit corresponding to a normal mode after the burn-in test.

1 more element

Dependencies are inferred from the claim text.

Facts

Application

16/859,798Filed 27 Apr 2020

Priority

JP 2019-11264418 Jun 2019

Published

24 Dec 2020

Term ends

Not estimatedThe source records don’t support an estimate.

Classification7 codes

G11C 29/12005
Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details: comprising voltage or current generators
G11C 29/006
Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation: at wafer scale level, i.e. wafer…
G11C 29/021
Detection or location of defective auxiliary circuits, e.g. defective refresh counters: in voltage or current generators
G11C 29/06
Detection or location of defective memory elements , e.g. cell constructio details, timing of test signals: acceleration testing

Semiconductor device and test method thereof

Life of this patent

Semiconductor device and test method thereof

Life of this patent

Abstract

Claims17