Nonvolatile memory apparatus for mitigating read disturbance and system using the same
AssigneeSK hynix Inc.
InventorsMoo Hui PARK, Seok Joon KANG, Jun Ho CHEON
Life of this patent
Estimating the term…
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AssigneeSK hynix Inc.
InventorsMoo Hui PARK, Seok Joon KANG, Jun Ho CHEON
Estimating the term…
A nonvolatile memory apparatus may include a memory cell, a bit line control circuit, and a word line control circuit. The memory cell may be coupled between a global bit line and a global word line. During a read operation, the bit line control circuit may provide a first high voltage to the global bit line and provide a second high voltage to the global bit line when snapback of the memory cell occurs. During the read operation, the word line control circuit may provide a second read supply voltage to the global word line and provide an anneal supply voltage to the global word line when snapback of the memory cell occurs.
A nonvolatile memory apparatus comprising:
An operation method of a nonvolatile memory apparatus, the method comprising:
Dependencies are inferred from the claim text.