Display controller to prevent visual artifacts with spread spectrum clocking
AssigneeIntel Corporation
InventorsNobuyuki Suzuki, Robert J. Johnston
Life of this patent
Estimating the term…
Abstract
A display controller and method for performing the same operations are described. In on embodiment, the display controller comprises a spread spectrum clock (SSC) modulator having a first input coupled to receive a non-SSC modulated clock and operable to generate a SSC modulated clock in response to the non-SSC modulated clock, a video data transfer portion coupled to receive the SSC modulated clock and operable to output data for display in response to the SSC modulated clock, and a second portion coupled to receive the non-SSC modulated clock.
Claims21
(canceled)
A display controller comprising:
- a clock generator to generate a modulated clock based on a base clock;
- first logic circuitry to be clocked by the modulated clock, the first logic circuitry including a first counter to be clocked by the modulated clock, the first logic circuitry to output an enable signal based on the first counter, the enable signal associated with transfer of video data to a display;
- and
- second logic circuitry to be clocked by the base clock, the second logic circuitry including a second counter to be clocked by the base clock, the second logic circuitry to output a synchronization signal based on the second counter, the synchronization signal to define a horizontal line access cycle, the second logic circuitry to reset the first counter and the second counter based on the base clock.
A system comprising:
- a display;
- memory to store video data;
- first logic circuitry to be clocked by a modulated clock, the first logic circuitry including a first counter to be clocked by the modulated clock, the first logic circuitry to output an enable signal based on the first counter, the enable signal associated with transfer of the video data to the display;
- and
- second logic circuitry to be clocked by a base clock used to generate the modulated clock, the second logic circuitry including a second counter to be clocked by the base clock, the second logic circuitry to output a synchronization signal based on the second counter, the synchronization signal to define a horizontal line access cycle, the second logic circuitry to reset the first counter and the second counter based on the base clock.
A method comprising:
- modulating a base clock to generate a modulated clock;
- generating, with first logic circuitry clocked with the modulated clock, an enable signal associated with transfer of video data to a display, the enable signal generated based on a first counter included in the first logic circuitry, the first counter clocked with the modulated clock;
- generating, with second logic circuitry clocked with the base clock, a synchronization signal to define a horizontal line access cycle, the synchronization signal generated based on a second counter included in the second logic circuitry, the second counter clocked with the base clock;
- and
- resetting the first counter and the second counter based on the base clock.
Dependencies are inferred from the claim text.