Buffer access for side-channel attack resistance

A cryptographic processing device, comprising:

• a cryptographic processing engine;
• a read buffer to store a first set of data blocks in a first memory address order and a second set of data blocks in a second memory address order;
• first circuitry to provide, to the cryptographic processing engine, the first set of data blocks in a first randomly selected cryptographic processing order that is a permutation of the first memory address order and to provide, to the cryptographic processing engine, the second set of data blocks in a second randomly selected cryptographic processing order that is a permutation of the second memory address order;
• and,
• second circuitry to store cryptographically processed versions of the first set of data blocks in an output buffer in a third memory address order that is based on the first randomly selected cryptographic processing order, the second circuitry also to store cryptographically processed versions of the second set of data blocks in the output buffer in a fourth memory address order that is based on the second randomly selected cryptographic processing order.

A method, comprising:

• providing, to an input buffer, a first set of data blocks in a first memory address order;
• providing, to the input buffer, a second set of data blocks in a second memory address order;
• providing, to a cryptographic processing engine, the first set of data blocks in a first randomly selected cryptographic processing order that is a permutation of the first memory address order;
• providing, to the cryptographic processing engine, the second set of data blocks in a second randomly selected cryptographic processing order that is a permutation of the second memory address order;
• storing cryptographically processed versions of the first set of data blocks in an output buffer in a third memory address order that is based on the first randomly selected cryptographic processing order;
• and,
• storing cryptographically processed versions of the second set of data blocks in the output buffer in a fourth memory address order that is based on the second randomly selected cryptographic processing order.