Hierarchical clock tree implementation

A method of constructing a hierarchical clock tree for an integrated circuit, the method comprising:

• constructing a clock distribution network at a first level;
• pushing the clock distribution network to partitions at a second level;
• calculating trial timing for the partitions at the second level;
• calculating combined timing of the clock distribution network and the trial timing for the partitions at the second level;
• calculating partition-level target constraints based on the combined timing of the clock distribution network and the trial timing for the partitions at the second level;
• and
• calculating revised timing at the partition level based on the target constraints.

A method of constructing a hierarchical clock tree for an integrated circuit, the method comprising:

• constructing a top-level clock distribution network;
• calculating distribution delays to endpoints of the clock distribution network;
• pushing the top-level clock distribution network down to a block level;
• constructing clock trees in blocks at the endpoints;
• calculating block-level insertion delays for the clock trees in blocks at the endpoints;
• combining the distribution delays with the block-level insertion delays to calculate clock tree insertion delays from a root of the top-level clock distribution network;
• calculating delay target constraints for the blocks based on the clock tree insertion delays from the root of the top-level clock distribution network;
• re-calculating block-level insertion delays based on the delay target constraints;
• merging the clock trees at the block level;
• and
• re-calculating the clock tree insertion delays from the root of the top-level clock distribution network.