Streaming engine with early and late address and loop count registers to track architectural state

A device comprising:

• a processing core;
• a level one (L1) cache memory;
• a level two (L2) cache memory;
• and
• a memory controller coupled to the processing core and to the L2 cache memory, wherein the memory controller includes:
• a first address generator configured to generate a first set of addresses;
• a memory interface coupled to the L2 cache memory and configured to retrieve a set of data based on the first set of addresses from the L2 cache memory via a data path that does not include the L1 cache memory;
• a buffer configured to store the set of data;
• a second address generator configured to generate a second set of addresses that correspond to the set of data in the buffer;
• and
• a holding register coupled to the processing core and configured to:
• receive a subset of the set of data based on the second set of addresses from the buffer;
• store the subset of the set of data;
• and
• provide the subset of the set of data to the processing core.