High-frequency and low-power l1 cache and associated access technique

A computer-implemented method for high-frequency and low-power level 1 (L1) cache access, the method comprising:

• inspecting a virtual address of an L1 data cache load instruction;
• searching a way predictor table using the metadata and the virtual address associated with the load instruction;
• and
• simultaneously with the searching, looking up a translation lookaside buffer (TLB) and cache tags of the L1 data cache.

A computer-implemented method for accelerating predictor training in a level 1 (L1) cache, the method comprising:

• priming metadata of a level 1 (L1) way predictor table with information learned using hardware prefetches prior to a load instruction;
• detecting a miss in a level 0 (L0) way predictor table and a hit in the L1 way predictor table;
• and
• refreshing the L0 way predictor table using metadata stored in the L1 way predictor table,
• wherein refreshing includes learning and storing one or more locations of a group of cache lines using the metadata stored in the L1 way predictor table.