Memory cache-line bounce reduction for shared i/o ring structures

A method comprising:

• receiving, by a producer processor, a first request associated with a first memory entry;
• storing, by the producer processor, the first request in a first slot of a shared ring buffer at a first offset, wherein the shared ring buffer includes an active ring buffer and a processed ring buffer that partially overlap in an overlapping region, the active ring buffer having a first plurality of slots and the processed ring buffer having a second plurality of slots;
• processing, by a consumer processor, the first request;
• writing, by the consumer processor, the processed first request in a second slot of the shared ring buffer at a second offset, wherein the second slot is located in the processed ring buffer outside of the overlapping region;
• receiving, by the producer processor, a second request associated with a second memory entry;
• and
• storing, by the producer processor, the second request in a third slot of the shared ring buffer, wherein the third slot is located in the overlapping region and adjacent to the first slot, and the third slot is in a different cache-line than the second slot.

A system comprising:

• a memory including a shared ring buffer having a plurality of slots, wherein the shared ring buffer includes an active ring buffer and a processed ring buffer that entirely overlap;
• a producer processor configured to:
• receive a first request associated with a first memory entry,
• store the first request in a first slot of the shared ring buffer,
• receive a second request associated with a second memory entry,
• store the second request in a second slot adjacent to the first slot;
• and
• a consumer processor configured to process the first request and write the processed first request in the shared ring buffer in a third slot at an offset, wherein the offset and the location of the first slot create a spacing between slots successively accessed by the consumer processor and the producer processor, wherein the third slot is in a different cache-line than the second slot.