US 2020/0401518 A1 · MEMORY CONTROLLER AND MEMORY SYSTEM HAVING THE MEMORY CONTROLLER

Abstract

There are provided a memory controller for performing a program operation and a memory system having the memory controller. The memory system includes a memory device including first and second planes each including a plurality of m-bit (m is a natural number of 2 or more) multi-level cell (MLC) blocks; and a memory controller for allocating a first address corresponding to a first MLC block of the m-bit MLC blocks in which first m-bit MLC data is to be programmed and a second address corresponding to a second MLC block of the m-bit MLC blocks in which second m-bit MLC data is to be programmed, and transmitting the allocated addresses and logical page data included in the m-bit MLC data to the memory device. The memory controller differently determines a transmission sequence of the logical page data according to whether the addresses correspond to the same plane among the planes.

Claims17

Dependent claims

A memory system comprising:

a memory device including first and second planes each including a plurality of M-bit multi-level cell (MLC) blocks, where M is a natural number of 2 or more;
and
a memory controller configured to:
allocate a first address corresponding to a first MLC block of the M-bit MLC blocks, in which first M-bit MLC data is to be programmed and a second address corresponding to a second MLC block of the M-bit MLC blocks, in which second M-bit MLC data is to be programmed, and
transmit the allocated addresses and plural pieces of logical page data included in the first and second M-bit MLC data to the memory device,
wherein the memory controller is further configured to differently determine a transmission sequence of the plural pieces of logical page data for the transmission according to whether the first and second addresses correspond to a same plane in the memory device.

3 more elements

A memory controller comprising:

a first buffer configured to store program data received from a host;
a data divider configured to divide the program data into first and second M-bit MLC data each including M pieces of logical page data, where M is a natural number of 2 or more;
an address allocator configured to allocate a first address corresponding to a first MLC block in which the first M-bit MLC data is to be programmed among a plurality of M-bit MLC blocks included in a memory device and a second address corresponding to a second MLC block in which the second M-bit MLC data is to be programmed among the plurality of M-bit MLC blocks;
a second buffer configured to output the M pieces of logical page data to the memory device according to a transmission sequence in which the M pieces of logical page data included in the first and second M-bit MLC data are queued;
and
a data sequence manager configured to differently determine the transmission sequence according to whether the first and second addresses correspond to a same plane included in the memory device, and queue the M pieces of logical page data in the second buffer according to the transmission sequence.

3 more elements

Dependencies are inferred from the claim text.

Memory controller and memory system having the memory controller

Life of this patent

Memory controller and memory system having the memory controller

Life of this patent

Abstract

Claims17