Topological quantum error correction using a data bus
AssigneeTuring Inc.
InventorsMichele Reilly, Simon Devitt
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AssigneeTuring Inc.
InventorsMichele Reilly, Simon Devitt
Estimating the term…
Described herein is a Quantum Computing device comprising a first and a second square patch of qubits, each of the first and second square patch of qubits representing a logical qubit and being in a joint quantum state corresponding to a surface code, the surface code having a distance of two or more. The first and second square patch of qubits have a side-length equal to the distance plus one qubits. The device furthermore comprises one or more chain of qubits prepared in a joint GHZ state serving as a data bus. The chain of qubits neighbors both the first and the second square patch of qubits and has a length equal to or greater than the sum of the two side-lengths.
A quantum computing device comprising:
A method for implementing a merge operation by performing an arbitrary length fault tolerant parity check in surface code quantum computing comprising:
Dependencies are inferred from the claim text.