Semiconductor memory devices and memory systems

A semiconductor memory device, comprising:

• a memory cell array including a plurality of memory cell rows, each of the plurality of memory cell rows including a plurality of dynamic memory cells;
• an error correction code (ECC) engine circuit;
• a refresh control circuit configured to generate refresh row addresses indicating one or more memory cell rows of the plurality of memory cell rows to be refreshed,
• a scrubbing control circuit configured to count the refresh row addresses and generate a scrubbing address that designates at least one first memory cell row of the plurality of memory cell rows,
• an error information register, and
• a control logic circuit configured to control the ECC engine circuit and the scrubbing control circuit,
• wherein the control logic circuit is configured to control the ECC engine circuit to cause the ECC engine circuit to generate an error generation signal based on performing a first ECC decoding on first sub-pages in the at least one first memory cell row of the plurality of memory cell rows in a scrubbing operation on the at least one first memory cell row and based on performing a second ECC decoding on second sub-pages in at least one second memory cell row of the plurality of memory cell rows in a normal read operation on the at least one second memory cell row,
• wherein the control logic circuit is further configured to record error information in the error information register and is configured to control the ECC engine circuit to cause the ECC engine circuit to skip an ECC encoding operation and an ECC decoding operation on at least one selected memory cell row of the at least one first memory cell row and the at least one second memory cell row based on referring to the error information, and
• wherein the error information at least indicates a quantity of error occurrences in the first memory cell row and the second memory cell row.

A memory system, comprising:

• a semiconductor memory device;
• and
• a memory controller configured to control the semiconductor memory device,
• wherein the semiconductor memory device includes
• a memory cell array including a plurality of memory cell rows, each of the plurality of memory cell rows including a plurality of dynamic memory cells;
• an error correction code (ECC) engine circuit;
• an error information register;
• and
• a control logic circuit configured to control the ECC engine circuit,
• wherein the control logic circuit is configured to control the ECC engine circuit to cause the ECC engine circuit to generate an error generation signal based on performing a first ECC decoding on first sub-pages in at least one first memory cell row of the plurality of memory cell rows in a scrubbing operation on the at least one first memory cell row and based on performing a second ECC decoding on second sub-pages in at least one second memory cell row of the plurality of memory cell rows in a normal read operation on the at least one second memory cell row,
• wherein the control logic circuit is further configured to record error information in the error information register and is configured to control the ECC engine circuit to cause the ECC engine circuit to skip an ECC encoding operation and an ECC decoding operation on at least one selected memory cell row of the at least one first memory cell row and the at least one second memory cell row based on referring to the error information,
• wherein the error information at least indicates a quantity of error occurrences in the first memory cell row and the second memory cell row,
• wherein the control logic circuit is configured to transmit error information associated with the at least one selected memory cell row as an error information signal to the memory controller.