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AssigneeIntel Corporation
InventorsRobert PAWLOWSKI, Joshua B. FRYMAN, Vincent CAVE, Eric M. SCHWARTZ, Ivan B. GANEV, Jason M. HOWARD, Ankit MORE, Shaden SMITH
Estimating the term…
Disclosed embodiments relate to hardware support for dual-memory atomic operations. In one example, a processor includes multiple cores, each including multiple multi-threaded pipelines (MTPs), each associated with a memory, an atomic unit (ATMU) to perform atomic operations and a write-combine buffer (WCB) to manage access to and locks of cache lines in the associated memory, each MTP including fetch and decode stages to fetch and decode an instruction having fields to specify first and second memory locations and an opcode calling for a first MTP to send a request to a second MTP of the multiple MTPs, the second MTP being associated with a memory to which the first memory location is mapped, and to perform an atomic dual-memory operation on the first and second memory locations using its associated ATMU and WCB to perform the request.
A processor comprising a plurality of cores, each core comprising:
A method performed by a processor comprising a plurality of cores each comprising a plurality of multi-threaded pipelines (MTPs), each MTP associated with a memory, an atomic unit (ATMU) to perform atomic operations and a write-combine buffer (WCB) to manage access to and locks of cache lines in its associated memory;
Dependencies are inferred from the claim text.