Loading patent…
AssigneeShanghai Zhaoxin Semiconductor Co., Ltd.
InventorsPenghao ZOU, Chen-Chen SONG, Kang-Kang ZHANG, Jianbin WANG
Estimating the term…
An instruction execution method suitable for being executed by a processor is provided. The first processor comprises a register alias table (RAT) and a reservation station. The instruction execution method includes: a register alias table receives a first micro-instruction and a second micro-instruction and issues the first micro-instruction and the second micro-instruction to the reservation station; and the reservation station assigns one of a plurality of execution units to execute the first micro-instruction, according to the first specific message of the first micro-instruction; and the reservation station assigns one of the execution units to execute the second micro-instruction, according to the second specific message of the second micro-instruction. When the reservation station determines that the execution units assigned for the first micro-instruction and the second micro-instruction are the same, the reservation station indicates that the second micro-instruction depends on the first micro-instruction.
An instruction execution method, suitable for being executed by a processor, wherein a first processor comprises a register alias table (RAT) and a reservation station, and the instruction execution method comprises:
An instruction execution device, comprising:
Dependencies are inferred from the claim text.