Method and system for saving power in a real time hardware processing unit

A method for saving power in a real time hardware processing unit, said method comprising:

• connecting a plurality of processing elements (PEs) in a matrix form;
• wherein a first set of the processing elements (PEs) comprises a multiple sets of the processing elements (PEs);
• wherein each set of the multiple sets of the processing elements (PEs) of the first set comprises a plurality of the processing elements (PEs) being adapted to connect in a row;
• wherein a second set of the processing elements (PEs) comprises a multiple sets of the processing elements (PEs);
• wherein each set of the multiple sets of the processing elements (PEs) of the second set comprises a plurality of the processing elements (PEs) being adapted to connect in a column;
• connecting a plurality of digital to analog converters (DAC) to each the set of the multiple sets of the processing elements (PEs) of the first set;
• wherein converting a plurality of digital inputs to a first analog output using each the digital to analog converter (DAC);
• sending the first analog output to the plurality of the processing elements (PEs) being adapted to connect in the row using each the digital to analog converters (DAC) such that the first analog output of the digital to analog converters (DAC) being an input to the plurality of the processing elements (PEs) being adapted to connect in the row;
• generating a second analog output corresponding to each the processing element (PE);
• wherein the second analog output of each the processing element (PE) is a product of the first analog output of the digital to analog converter (DAC) and a digital weight input;
• generating an anlaog dotproduct output using each the set of the multiple sets of the processing elements (PEs) of the second set;
• connecting each the set of the multiple sets of the processing elements (PEs) of the second set using an analog to digital converter (ADC);
• wherein converting the analog dotproduct output to a digital output using each the analog to digital converter (ADC).

A system for saving power in a real time hardware processing unit, said system comprising:

• a first circuit and a second circuit;
• wherein the first circuit is substantially identical to the second circuit;
• wherein the first circuit comprising:
• a plurality of binary weighted capacitors;
• a plurality of switches;
• wherein the plurality of switches are adapted to connect the corresponding plurality of binary weighted capacitors;
• a two phase non-overlapping clock signal input defined a phase one non-overlapping clock signal input, a phase two non-overlapping clock signal input;
• an analog input defined a first analog input (Vinp), a second analog input (Vinn);
• a plurality of digital input bits;
• wherein each the digital input bit is adapted to connect the corresponding switch such that each the digital input bit is adapted to control the corresponding switch;
• wherein a most significant bit of the plurality of digital input bits determines a first analog input (Vinp) if the most significant bit is zero;
• wherein the most significant bit of the plurality of digital input bits determines a second analog input (Vinn) if the most significant bit is one;
• the plurality of binary weighted capacitors adapted to connect the first analog input during the phase 1 non-overlapping clock signal input if the most significant bit of the plurality of digital inputs is zero and the plurality of digital inputs of the corresponding plurality of binary weighted capacitors are ones;
• and the plurality of binary weighted capacitors adapted to reset during the phase 1 non-overlapping clock signal input if the plurality of digital inputs of the corresponding plurality of binary weighted capacitors are zero;
• or
• the plurality of binary weighted capacitors adapted to connect the second analog input during the phase 1 non-overlapping clock signal input if the most significant bit of the plurality of digital inputs is one and the plurality of digital inputs of the corresponding plurality of binary weighted capacitors are ones;
• and the plurality of binary weighted capacitors adapted to reset during the phase 1 non-overlapping clock signal input if the plurality of digital inputs of the corresponding plurality of binary weighted capacitors are zeros;
• and
• the plurality of capacitors adapted to connect in parallel during the phase 2 non-overlapping clock signal input such that the plurality of capacitors generate a first analog output (206a);
• wherein the second circuit comprising:
• a plurality of binary weighted capacitors;
• a plurality of switches;
• wherein the plurality of switches are adapted to connect the corresponding plurality of binary weighted capacitors;
• a two phase non-overlapping clock signal input defined as a phase one non-overlapping clock signal input, a phase two non-overlapping clock signal input;
• a differential analog input defined as a first analog input (Vinp), a second analog input (Vinn);
• a plurality of digital input bits;
• wherein each the digital input bit is adapted to connect the corresponding switch such that each the digital input bit is adapted to control the corresponding switch;
• wherein a most significant bit of the plurality of digital input bits determines a second analog input (Vinn) if the most significant bit is zero;
• wherein the most significant bit of the plurality of digital input bits determines a first analog input (Vinp) if the most significant bit is one;
• the plurality of binary weighted capacitors adapted to connect the first analog input during the phase 1 non-overlapping clock signal input if the most significant bit of the plurality of digital inputs is one and the plurality of digital inputs of the corresponding plurality of binary weighted capacitors are ones;
• and the plurality of binary weighted capacitors adapted to reset during the phase 1 non-overlapping clock signal input if the plurality of digital inputs of the corresponding plurality of binary weighted capacitors are zero;
• or
• the plurality of binary weighted capacitors adapted to connect the second analog input during the phase 1 non-overlapping clock signal input if the most significant bit of the plurality of digital inputs is zero and the plurality of digital inputs of the corresponding plurality of binary weighted capacitors are ones;
• and the plurality of binary weighted capacitors adapted to reset during the phase 1 non-overlapping clock signal input if the plurality of digital inputs of the corresponding plurality of binary weighted capacitors are zeros;
• and
• the plurality of capacitors adapted to connect in parallel during the phase 2 non-overlapping clock signal input such that the plurality of capacitors generate a second analog output.

A system for saving power in a real time hardware processing unit, said system comprising:

• A first circuit and a second circuit;
• wherein the first circuit is substantially identical to the second circuit;
• each the circuit comprising:
• a main resistive string;
• the main resistive string comprising a plurality of resistors, a plurality of switches wherein the plurality of resistors are connected in series;
• wherein the plurality of switches of the main resistive string are operatively connected to corresponding a plurality of nodes of the main resistive string;
• wherein the plurality of switches of the main resistive string are adapted to be positioned in a matrix form;
• wherein the main resistive string is adapted to connect between an analog input voltage and a common mode voltage;
• wherein the main resistive string is adapted to divide the analog input voltage into a plurality of analog voltages corresponding to the plurality of nodes of the main resistive string;
• a sub resistive string;
• the sub resistive string comprising a plurality of resistors, a plurality of switches;
• wherein the plurality of resistors are connected in series;
• wherein the plurality of switches of the sub resistive string are operatively connected to corresponding a plurality of nodes of the sub resistive string;
• wherein the plurality of switches of the sub resistive string are adapted to be positioned in a matrix form;
• wherein the sub resistive string is operatively connected to a first node of the plurality of nodes of the main resistive string such that the sub resistive string is adapted to divide the voltage at the first node of the plurality of nodes of the main resistive string into a plurality of analog voltages corresponding to the plurality of nodes of the sub resistive string;
• a capacitor;
• wherein a top plate of the capacitor is operatively connected to any one of the nodes of the main resistive string using the matrix form of switches of the main resistive string during ‘ON’ period of a clock and a bottom plate of the capacitor is operatively connected to any one of the nodes of the sub resistive string using the matrix form of switches of the sub resistive string during ‘ON’ period of the clock such that an analog voltage output is generated across the two plates of the capacitor;
• wherein the analog voltage output is proportional to a product of the analog input voltage and a digital input.