Clock generator for adjusting jitter characteristics and operation power, semiconductor device including the clock generator, and operating method of the clock generator

A clock generator comprising:

• a phase detector configured to detect a phase difference between an input clock and a signal obtained by dividing an output clock;
• a voltage generator configured to generate a control voltage having a level based on the phase difference;
• a voltage-to-current converter comprising a resistor circuit comprising a plurality of resistors, the voltage-to-current converter being configured to convert the control voltage into an internal current having a level based on a resistance value of the resistor circuit, the resistance value being set based on first control information;
• and
• an oscillation circuit comprising a capacitor circuit comprising a plurality of capacitors, the oscillation circuit generating the output clock having a frequency based on the level of the internal current and a capacitance value of the capacitor circuit, the capacitance value being set based on second control information;
• a digital-to-analog converter connected to an output of the voltage-to-current converter to generate a first current having a level proportional to the internal current from the voltage-to-current converter in response to receiving a control bit,
• wherein the clock generator is configured to maintain a frequency value and vary a jitter characteristic of the output clock in response to the first control information and the second control information, and
• wherein the oscillation circuit is configured to receive the first current as a supply current from the digital-to-analog converter.

A semiconductor device comprising:

• a clock generator configured to receive an input clock to generate an output clock having a target frequency;
• and
• a control logic configured to output control information for controlling a jitter characteristic of the output clock of the clock generator,
• wherein the clock generator comprises a voltage controlled oscillator configured to generate the output clock having a frequency based on a control voltage generated based on a phase difference between the input clock and a signal obtained by dividing the output clock, and
• wherein the voltage controlled oscillator is configured to receive the control information and decrease a jitter of the output clock having the target frequency in response to the control information having a first value, and to increase the jitter of the output clock having the target frequency in response to the control information having a second value.