Binary Arithmetic Decoder and Binary Arithmetic Decoding Device
AssigneeNTT Electronics Corporation
InventorsManabu Tagaki, Takashi Matsumoto
Life of this patent
Estimating the term…
Loading patent…
AssigneeNTT Electronics Corporation
InventorsManabu Tagaki, Takashi Matsumoto
Estimating the term…
A binary arithmetic device includes an LPS/MPS determining unit that determines, using a context variable, a range length, and an offset, whether a code is an inferior probability code or a superior probability code, a renormalization processing unit that performs renormalization processing on the range length and the offset, and a context-variable calculating unit that derives the binary data of the code using a determination result and updates the context variable according to the determination result. The renormalization processing unit 15 includes a first renormalizing unit and a second renormalizing unit and a selecting unit that selects, according to the determination result, an output of the first renormalizing unit or an output of the second renormalizing unit.
A binary arithmetic decoder comprising:
A binary arithmetic decoding device that decodes input encoded data into binary data and outputs the binary data, the binary arithmetic decoding device comprising:
Dependencies are inferred from the claim text.