Snapback clamps for esd protection with voltage limited, centralized triggering scheme

An integrated circuit (IC) comprising:

• a first pad configured to receive a signal;
• a first MOS transistor coupled to the first pad, wherein the first MOS transistor is configured to transition to snapback mode when voltage at the first pad exceeds a snapback trigger threshold for the first MOS transistor;
• a second MOS transistor coupled to a first conductor, wherein the second MOS transistor is configured to transition to snapback mode when voltage at the first conductor exceeds a snapback trigger voltage threshold for the second MOS transistor;
• a trigger circuit configured to generate a trigger voltage VT for lowering the first MOS transistor's snapback trigger voltage threshold and for lowering the second MOS transistor's snapback trigger voltage threshold;
• a voltage limiter configured to limit the trigger voltage VT.