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US 2020/0395487 A1Published application
Memory Devices and Methods of Manufacture Thereof
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsAlexander Kalnitsky, Hsiao-Chin Tuan, Felix Ying-Kit Tsui, Hau-Yan Lu
Life of this patent
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Abstract
Representative methods of manufacturing memory devices include forming a transistor with a gate disposed over a workpiece, and forming an erase gate with a tip portion extending towards the workpiece. The transistor includes a source region and a drain region disposed in the workpiece proximate the gate. The erase gate is coupled to the gate of the transistor.
Claims20
A memory device, comprising:
- a first active area, a second active area, and a third active area in a substrate, the first active area having a recess;
- a first isolation region interposed between the first active area and the second active area;
- a second isolation region interposed between the second active area and the third active area;
- a dielectric layer over the first active area, the second active area, the third active area, the first isolation region, and the second isolation region, the dielectric layer extending into the recess in the first active area;
- and
- a conductive electrode over the dielectric layer over the first active area, the second active area, the third active area, the first isolation region, and the second isolation region, wherein the conductive electrode comprises a first plate of a first capacitor over the first active area, a gate of a transistor over second active area, and a first plate of a second capacitor over the third active area, wherein the first active area forms a second plate of the first capacitor, wherein the third active area forms a second plate of the second capacitor.
3 more elements
A memory device, comprising:
- a first capacitor in a first region of a substrate, wherein a first plate of the first capacitor comprises a first doped region of the substrate;
- a second capacitor in a second region of the substrate, the second capacitor being coupled in series with the first capacitor, wherein a first plate of the second capacitor comprises a second doped region of the substrate;
- and
- a transistor in a third region of the substrate, source/drain regions and a channel region of the transistor comprising a third doped region of the substrate, wherein a second plate of the first capacitor, a second plate of the second capacitor, and a gate of the transistor comprises a single continuous conductive layer, wherein the second plate of the first capacitor comprises a tip portion extending into a recess in the first plate of the first capacitor.
1 more element
A memory device, comprising:
- a first capacitor comprising a first plate, a second plate, and a first dielectric region interposed between the first plate and the second plate, the first plate comprising a first doped region of a substrate, the first dielectric region and the second plate filling a recess in the first doped region;
- a second capacitor comprising a third plate, a fourth plate, and a second dielectric region interposed between the third plate and the fourth plate, the third plate comprising a second doped region of the substrate;
- and
- a transistor comprising source/drain regions, a channel region interposed between the source/drain regions, and a gate electrode overlying the channel region, wherein the second plate, the fourth plate, and the gate electrode comprise a conductive layer, the conductive layer extending continuously over the first plate, the third plate, and the channel region.
1 more element
Dependencies are inferred from the claim text.