Thin poly field plate design

A transistor device, comprising:

• a source region and a drain region disposed within a substrate;
• a gate electrode disposed between the source region and the drain region;
• a spacer continuously extending between a first outermost sidewall that is between the gate electrode and the drain region and a second outermost sidewall directly over the gate electrode;
• a field plate disposed along an upper surface and a sidewall of the spacer;
• a first inter-level dielectric (ILD) layer overlying the substrate, the gate electrode, and the field plate;
• and
• a first conductive contact contacting a first horizontally extending surface of the field plate between the gate electrode and the drain region, wherein the first conductive contact has a sidewall that is laterally separated from a sidewall of the field plate by the first ILD layer.

A transistor device, comprising:

• a source region and a drain region disposed within a substrate;
• a gate electrode disposed between the source region and the drain region;
• a field plate disposed along an upper surface and a sidewall of the gate electrode and continuously extending between a first outermost sidewall that is between the gate electrode and the drain region and a second outermost sidewall directly over the gate electrode;
• a first inter-level dielectric (ILD) layer overlying the substrate, the gate electrode, and the field plate;
• and
• a first conductive contact contacting a first horizontally extending surface of the field plate between the gate electrode and the drain region, wherein the first conductive contact has a sidewall that is laterally separated from a sidewall of the field plate by the first ILD layer.