US 2020/0395341 A1 · SEMICONDUCTOR MEMORY DEVICE

Abstract

A semiconductor memory device includes a memory chip. The memory chip includes a first region including a plurality of first memory cells and second memory cells, a second region different from the first region, a plurality of first word lines stacked apart from each other in a first direction in the first and second regions, a first pillar including a first semiconductor layer extending through the first word lines, and a first insulator layer provided between the first semiconductor layer and the first word lines, in the first region, the first memory cells being located at intersections of the first pillar with the first word lines, a first bonding pad in the second region, and a first transistor between the first word lines and the first bonding pad, and connected between one of the first word lines and the first bonding pad, in the second region.

Claims20

Dependent claims

A semiconductor memory device comprising:

a memory chip,
wherein the memory chip includes:
a first region including a plurality of first memory cells and second memory cells;
a second region different from the first region;
a plurality of first word lines stacked apart from each other in a first direction in the first region and the second region;
a first pillar including a first semiconductor layer extending through the plurality of first word lines, and a first insulator layer provided between the first semiconductor layer and the plurality of first word lines, in the first region, the first memory cells being located at intersections of the first pillar with the first word lines;
a first bonding pad in the second region;
and
a first transistor between the plurality of first word lines and the first bonding pad, and connected between one of the first word lines and the first bonding pad, in the second region.

6 more elements

A semiconductor memory device comprising:

a memory chip,
wherein the memory chip includes:
a plurality of first memory cells and second memory cells;
a plurality of first word lines stacked apart from each other in a first direction;
a first pillar including a first semiconductor layer extending through the plurality of first word lines, and a first insulator layer provided between the first semiconductor layer and the plurality of first word lines, the first memory cells being located at intersections of the first pillar with the first word lines;
a first bit line electrically connected to the first semiconductor layer;
a first transistor electrically connected to the first bit line;
and
a first bonding pad electrically connected to the first bit line via the first transistor.

6 more elements

Dependencies are inferred from the claim text.

Semiconductor memory device

Life of this patent

Semiconductor memory device

Life of this patent

Abstract

Claims20